From: Nina Engelhardt Date: Sun, 11 Aug 2013 21:07:07 +0000 (+0200) Subject: add mist synthesis mode to build X-Git-Tag: 24jan2021_ls180~2099^2~443^2~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ebbfa63bf0ef52be06a79a9d8f01af18dbb10d9;p=litex.git add mist synthesis mode to build --- diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 72a6435a..0973545b 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -77,6 +77,10 @@ class AlteraQuartusPlatform(GenericPlatform): tools.mkdir_noerror(build_dir) os.chdir(build_dir) + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + self.finalize(fragment) + v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 62ddcf8f..17c8752a 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,4 +1,3 @@ -from copy import copy import os, argparse from migen.fhdl.std import * @@ -138,11 +137,6 @@ class ConstraintManager: def get_platform_commands(self): return self.platform_commands - def save(self): - return copy(self.available), copy(self.matched), copy(self.platform_commands) - - def restore(self, backup): - self.available, self.matched, self.platform_commands = backup class GenericPlatform: def __init__(self, device, io, default_crg_factory=None, name=None): @@ -167,6 +161,12 @@ class GenericPlatform: def finalize(self, fragment, *args, **kwargs): if self.finalized: raise ConstraintError("Already finalized") + # if none exists, create a default clock domain and drive it + if not fragment.clock_domains: + if self.default_crg_factory is None: + raise NotImplementedError("No clock/reset generator defined by either platform or user") + crg = self.default_crg_factory(self) + fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True @@ -206,41 +206,21 @@ class GenericPlatform: named_pc.append(template.format(**name_dict)) return named_sc, named_pc - def get_verilog(self, fragment, **kwargs): + def _get_source(self, fragment, gen_fn): if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() - # We may create a temporary clock/reset generator that would request pins. - # Save the constraint manager state so that such pin requests disappear - # at the end of this function. - backup = self.constraint_manager.save() - try: - # if none exists, create a default clock domain and drive it - if not fragment.clock_domains: - if self.default_crg_factory is None: - raise NotImplementedError("No clock/reset generator defined by either platform or user") - crg = self.default_crg_factory(self) - frag = fragment + crg.get_fragment() - else: - frag = fragment - # finalize - self.finalize(fragment) - # generate Verilog - src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), - return_ns=True, create_clock_domains=False, **kwargs) - named_sc, named_pc = self._resolve_signals(vns) - finally: - self.constraint_manager.restore(backup) + # generate source + src, vns = gen_fn(fragment) + named_sc, named_pc = self._resolve_signals(vns) return src, named_sc, named_pc + + def get_verilog(self, fragment, **kwargs): + return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(), + return_ns=True, create_clock_domains=False, **kwargs)) def get_edif(self, fragment, cell_library, vendor, device, **kwargs): - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - # finalize - self.finalize(fragment) - # generate EDIF - src, vns = edif.convert(fragment, self.constraint_manager.get_io_signals(), cell_library, vendor, device, return_ns=True, **kwargs) - named_sc, named_pc = self._resolve_signals(vns) - return src, named_sc, named_pc + return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(), + cell_library, vendor, device, return_ns=True, **kwargs)) def build(self, fragment): raise NotImplementedError("GenericPlatform.build must be overloaded") diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 31f6f65c..8df2cfba 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -4,6 +4,7 @@ from decimal import Decimal from migen.fhdl.std import * from migen.fhdl.specials import SynthesisDirective from migen.genlib.cdc import * +from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * from mibuild.crg import SimpleCRG @@ -167,6 +168,10 @@ class XilinxISEPlatform(GenericPlatform): tools.mkdir_noerror(build_dir) os.chdir(build_dir) + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + self.finalize(fragment) + if mode == "verilog": v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" @@ -176,7 +181,11 @@ class XilinxISEPlatform(GenericPlatform): if run: _run_ise(build_name, ise_path, source, mode="verilog") - if mode == "edif": + if mode == "mist": + from mist import synthesize + synthesize(fragment, self.constraint_manager.get_io_signals()) + + if mode == "edif" or mode == "mist": e_src, named_sc, named_pc = self.get_edif(fragment) e_file = build_name + ".edif" tools.write_to_file(e_file, e_src) @@ -184,6 +193,7 @@ class XilinxISEPlatform(GenericPlatform): tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) if run: _run_ise(build_name, ise_path, source, mode="edif") + os.chdir("..") def build_arg_ns(self, ns, *args, **kwargs):