From: Kyrylo Tkachov Date: Tue, 6 Jun 2017 13:26:46 +0000 (+0000) Subject: [AArch64] Allow const0_rtx operand for atomic compare-exchange patterns X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ebcc903bf03705099cd4b50231dc8fe444d70b9;p=gcc.git [AArch64] Allow const0_rtx operand for atomic compare-exchange patterns * config/aarch64/atomics.md (atomic_compare_and_swap expander): Use aarch64_reg_or_zero predicate for operand 4. (aarch64_compare_and_swap define_insn_and_split): Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. (aarch64_store_exclusive): Likewise for operand 2. * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test. From-SVN: r248921 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ad09804a1d0..5b27621664b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-06 Kyrylo Tkachov + + * config/aarch64/atomics.md (atomic_compare_and_swap expander): + Use aarch64_reg_or_zero predicate for operand 4. + (aarch64_compare_and_swap define_insn_and_split): + Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. + (aarch64_store_exclusive): Likewise for operand 2. + 2017-06-06 Thomas Preud'homme * config/arm/arm.c (arm_compute_save_reg_mask): Rename into ... diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 09d441075f0..27fc1933ce3 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -25,7 +25,7 @@ (match_operand:ALLI 1 "register_operand" "") ;; val out (match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory (match_operand:ALLI 3 "general_operand" "") ;; expected - (match_operand:ALLI 4 "register_operand" "") ;; desired + (match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f @@ -45,7 +45,7 @@ (set (match_dup 1) (unspec_volatile:SHORT [(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected - (match_operand:SHORT 3 "register_operand" "r") ;; desired + (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -69,7 +69,7 @@ (set (match_dup 1) (unspec_volatile:GPI [(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect - (match_operand:GPI 3 "register_operand" "r") ;; desired + (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -534,7 +534,7 @@ (unspec_volatile:SI [(const_int 0)] UNSPECV_SX)) (set (match_operand:ALLI 1 "aarch64_sync_memory_operand" "=Q") (unspec_volatile:ALLI - [(match_operand:ALLI 2 "register_operand" "r") + [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") (match_operand:SI 3 "const_int_operand")] UNSPECV_SX))] "" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a23dc7a184a..663f21e2b4a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-06 Kyrylo Tkachov + + * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test. + 2017-06-06 Richard Biener PR tree-optimization/80974 diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c new file mode 100644 index 00000000000..15606b68990 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int *a) +{ + int x = 3; + return __atomic_compare_exchange_n (a, &x, 0, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} + +/* { dg-final { scan-assembler "stxr\\tw\[0-9\]+, wzr,.*" } } */ +/* { dg-final { scan-assembler-not "mov\\tw\[0-9\]+, 0" } } */