From: riktw <rik@justanotherelectronicsblog.com>
Date: Tue, 27 Aug 2019 20:20:02 +0000 (+0200)
Subject: Added support for building for Arty A7 boards
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ebd6fc1f79a2695cd8e6bf4fe4d425c79e02b2e;p=microwatt.git

Added support for building for Arty A7 boards
---

diff --git a/fpga/arty_a7-35.xdc b/fpga/arty_a7-35.xdc
new file mode 100644
index 0000000..0e62736
--- /dev/null
+++ b/fpga/arty_a7-35.xdc
@@ -0,0 +1,7 @@
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }];
+
+set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { reset_n }]; #mapped to SW0
+
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; 
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
diff --git a/microwatt.core b/microwatt.core
index 7263794..f365b91 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -48,6 +48,12 @@ filesets:
     files:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      
+  arty_a7-35:
+    files:
+      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+  
 
 targets:
   nexys_a7:
@@ -65,6 +71,14 @@ targets:
     tools:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
+    
+  arty_a7-35:
+    default_tool: vivado
+    filesets: [core, arty_a7-35, soc]
+    parameters : [memory_size, ram_init_file]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : toplevel
 
   synth:
     filesets: [core]