From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 6 Oct 2020 01:06:51 +0000 (-0700)
Subject: add test case for divweu regression
X-Git-Tag: 24jan2021_ls180~223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ec0a156cb9a210b1c00e0830e8d8c0a2ad22341;p=soc.git

add test case for divweu regression
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 188196e7..bd22c81d 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -11,6 +11,15 @@ from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
 
 
 class DivTestCases(TestAccumulatorBase):
+    def case_divweu_regression(self):
+        # simulator is wrong, FSM and power-instruction-analyzer both correct
+        lst = ["divweu 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1
+        initial_regs[2] = 0xffffffffffffffff
+        with Program(lst, bigendian) as prog:
+            self.add_case(prog, initial_regs)
+
     def case_divwe_regression(self):
         # div FU and power-instruction-analyzer both correctly return 0
         # hitting behavior undefined by Power v3.1 spec, need to adjust