From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Sep 2018 15:46:24 +0000 (+0100)
Subject: zeroing set to 0
X-Git-Tag: convert-csv-opcode-to-binary~5013
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ecd7654c29c3c2f9f004fc3e7899c8d998404b7;p=libreriscv.git

zeroing set to 0
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 6ce30adde..ea10abce9 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -416,7 +416,7 @@ integer registers (as a future option)
   register itself.
 * zeroing is either 1 or 0, and if set to 1, the operation must
   place zeros in any element position where the predication mask is
-  set to zero.  If zeroing is set to 1, unpredicated elements *must*
+  set to zero.  If zeroing is set to 0, unpredicated elements *must*
   be left alone.  Some microarchitectures may choose to interpret
   this as skipping the operation entirely.  Others which wish to
   stick more closely to a SIMD architecture may choose instead to