From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 7 Sep 2020 10:58:30 +0000 (+0100)
Subject: whoops truncated the mb and me fields
X-Git-Tag: semi_working_ecp5~153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4efb9d5f7991323c4e5f6f4612072f745399a2f6;p=soc.git

whoops truncated the mb and me fields
---

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 05969d31..8e5f9ecd 100644
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -100,9 +100,9 @@ class Driver(Elaboratable):
         # clear left?
         with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCL)):
             with m.If(rec.is_32bit):
-                comb += mb.eq(m_fields.MB[0:-1])
+                comb += mb.eq(m_fields.MB)
             with m.Else():
-                comb += mb.eq(md_fields.mb[0:-1])
+                comb += mb.eq(md_fields.mb)
         with m.Else():
             with m.If(rec.is_32bit):
                 comb += mb.eq(b[0:6])
@@ -117,9 +117,9 @@ class Driver(Elaboratable):
         # clear right?
         with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCR)):
             with m.If(rec.is_32bit):
-                comb += me.eq(m_fields.ME[0:-1])
+                comb += me.eq(m_fields.ME)
             with m.Else():
-                comb += me.eq(md_fields.me[0:-1])
+                comb += me.eq(md_fields.me)
         with m.Else():
             with m.If(rec.is_32bit):
                 comb += me.eq(b[0:6])