From: Andrey Miroshnikov Date: Wed, 15 Jun 2022 22:39:17 +0000 (+0100) Subject: Initial svp64 doc structure with quick notes from meeting X-Git-Tag: opf_rfc_ls005_v1~1763 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f02d7668ab90b50e355bdb8b04153fe98b1b523;p=libreriscv.git Initial svp64 doc structure with quick notes from meeting --- diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex new file mode 100644 index 000000000..41824537f --- /dev/null +++ b/svp64-primer/summary.tex @@ -0,0 +1,31 @@ +\section{Summary} +Specification for hardware for-loop that ONLY uses scalar instructions + + +Existing SIMD technologies are complex [examples], and +https://www.sigarch.org/simd-instructions-considered-harmful/ +(actually much worse) +AVX512 example requires setup instructions (and data organisation), which means real code baloons. At the start/end need to deal with memory boundaries. + + + +SVP64, is a specification designed to rival existing SIMD implementations by: +\begin{itemize} + \item Simplify hardware design + \item Reducing maintenance overhead + \item Simplify manual assembler hand optimisation + \item Easier for compilers, coders, documentation + \item Time to support platform is a fraction of conventional SIMD (Less money R\&D, faster to deliver) +\end{itemize} + +- Intel SIMD is designed to be more capable and has more features, and thus has a greater complexity (?) + + +- What are we going to gain? + +-for loop, increment registers RT, RA, RB +-few instructions, easier to implement and maintain +-example assembly code +-ARM has already started to add to libC SVE2 support + +1970 x86 comparison \ No newline at end of file diff --git a/svp64-primer/svp64-primer.tex b/svp64-primer/svp64-primer.tex new file mode 100644 index 000000000..8a5fef1c1 --- /dev/null +++ b/svp64-primer/svp64-primer.tex @@ -0,0 +1,14 @@ +\documentclass[a4paper, 10pt]{article} +\usepackage[utf8]{inputenc} + +\title{(DRAFT) SVP64 Primer} + +\author{Andrey Miroshnikov, ...} + +\begin{document} +\maketitle + +\input{summary} +%\input{...} + +\end{document}