From: Eddie Hung <eddie@fpgeh.com> Date: Fri, 22 May 2020 04:39:13 +0000 (-0700) Subject: abc9_ops: update comment X-Git-Tag: working-ls180~543 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f0f32116956782059d415a13ac52bf056634d6f;p=yosys.git abc9_ops: update comment --- diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 10c980f73..8d55b18a0 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -547,7 +547,7 @@ void mark_scc(RTLIL::Module *module) // For every unique SCC found, (arbitrarily) find the first // cell in the component, and replace its output connections // with a new wire driven by the old connection but with a - // special (* abc9_scc *) attribute set (which is used by + // special (* abc9_keep *) attribute set (which is used by // write_xaiger to break this wire into PI and POs) pool<RTLIL::Const> ids_seen; for (auto cell : module->cells()) {