From: lkcl Date: Sat, 23 Apr 2022 18:33:15 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2612 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f1f6d92a680c7198eb2455438ade469c23bcf52;p=libreriscv.git --- diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 2973944e1..a481f5e21 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -46,8 +46,8 @@ fashion that is hidden from the user, behind a consistent, stable ISA API. For the Opcode map (XO Field) see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357. -Proposed is the addition of `msubed` (**DRAFT, NOT APPROVED**) which is -in `110110`. A corresponding `madded` is proposed for `110010` +Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) which is +in `110010`. | 110000 | 110001 | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 | | ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ | @@ -62,7 +62,7 @@ used with the additional bit set for determining RS. | Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding) | | Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding) | | Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding) | -| EXTRA2_MODE | `18` | used by `msubed` and `madded` for RS | +| EXTRA2_MODE | `18` | used by `madded` for RS | When `EXTRA2_MODE` is set to zero, the implicit RS register takes its Vector/Scalar setting from Rdest_EXTRA2, and takes @@ -83,8 +83,8 @@ The pseudocode for `madded RT, RA, RB, RC` is: RT <- sum[64:127] RS <- sum[0:63] # RS is either RC or RT+VL -Again RC is zero-extended (not shifted), the 128-bit product added -to it; the lower half of the result stored in RT and the upper half +RC is zero-extended (not shifted), the 128-bit product added +to it; the lower half of that result stored in RT and the upper half in RS. The differences here to `maddhdu` are that `maddhdu` stores the upper