From: Alan Lawrence Date: Fri, 19 Dec 2014 17:44:36 +0000 (+0000) Subject: [AArch64 1/3] Don't disparage add/sub in SIMD registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f2962fd47452bfe0d343392f6417c08fa221083;p=gcc.git [AArch64 1/3] Don't disparage add/sub in SIMD registers * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize SIMD reg variant. From-SVN: r218958 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19b33e719cc..f27d6986961 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-12-19 Alan Lawrence + + * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize + SIMD reg variant. + 2014-12-19 Martin Liska PR ipa/63569 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 12532c1675f..3e8434602b9 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1434,10 +1434,10 @@ (define_insn "*adddi3_aarch64" [(set - (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w") + (match_operand:DI 0 "register_operand" "=rk,rk,rk,w") (plus:DI - (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w") - (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))] + (match_operand:DI 1 "register_operand" "%rk,rk,rk,w") + (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))] "" "@ add\\t%x0, %x1, %2 @@ -1908,9 +1908,9 @@ ) (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=rk,!w") - (minus:DI (match_operand:DI 1 "register_operand" "r,!w") - (match_operand:DI 2 "register_operand" "r,!w")))] + [(set (match_operand:DI 0 "register_operand" "=rk,w") + (minus:DI (match_operand:DI 1 "register_operand" "r,w") + (match_operand:DI 2 "register_operand" "r,w")))] "" "@ sub\\t%x0, %x1, %x2