From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 17:45:00 +0000 (+0000)
Subject: add vss/vdd as pins, gets the net into the VST
X-Git-Tag: LS180_RC3~27^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f3fce32074946c452fe9089cec271a6d5843e59;p=soclayout.git

add vss/vdd as pins, gets the net into the VST
---

diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py
index 07a89a9..d485d56 100644
--- a/experiments10_verilog/pll.py
+++ b/experiments10_verilog/pll.py
@@ -214,7 +214,7 @@ def _load():
     with UpdateSession():
         cell.setAbutmentBox(Box(
             #u(0.0), u(0.0), u(13.5), u(2.025),
-            u(0.0), u(0.0), u(space*100), u(space*25),
+            u(0.0), u(0.0), u(space*125), u(space*25),
         ))
         nets = {
             #'*': Net.create(cell, '*'),
@@ -238,14 +238,16 @@ def _load():
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
         nets['vdd'].setType( Net.Type.POWER )
+        nets['vdd'].setDirection( Net.Direction.IN )
         nets['vss'].setType( Net.Type.GROUND )
+        nets['vss'].setDirection( Net.Direction.IN )
 
         # create series of stepped pins
         x = space*20
         wid = space
         step = wid*5
         for cname in ['ref_v', 'div_out_test', 'a0', 'a1', 'vco_test_ana',
-                      'out_v']:
+                      'out_v', 'vdd', 'vss']:
             net = nets[cname]
             pin = Vertical.create(
                 net, tech.getLayer('metal1'),
diff --git a/experiments9/pll.py b/experiments9/pll.py
index 07a89a9..d485d56 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -214,7 +214,7 @@ def _load():
     with UpdateSession():
         cell.setAbutmentBox(Box(
             #u(0.0), u(0.0), u(13.5), u(2.025),
-            u(0.0), u(0.0), u(space*100), u(space*25),
+            u(0.0), u(0.0), u(space*125), u(space*25),
         ))
         nets = {
             #'*': Net.create(cell, '*'),
@@ -238,14 +238,16 @@ def _load():
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
         nets['vdd'].setType( Net.Type.POWER )
+        nets['vdd'].setDirection( Net.Direction.IN )
         nets['vss'].setType( Net.Type.GROUND )
+        nets['vss'].setDirection( Net.Direction.IN )
 
         # create series of stepped pins
         x = space*20
         wid = space
         step = wid*5
         for cname in ['ref_v', 'div_out_test', 'a0', 'a1', 'vco_test_ana',
-                      'out_v']:
+                      'out_v', 'vdd', 'vss']:
             net = nets[cname]
             pin = Vertical.create(
                 net, tech.getLayer('metal1'),