From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 May 2019 09:36:28 +0000 (-0700)
Subject: shift register inference before mux
X-Git-Tag: working-ls180~1208^2~286
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f44e3399ba6c959c830943c44c4ad728be895fa;p=yosys.git

shift register inference before mux
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ec7768ffe..3cee81a7b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -266,9 +266,6 @@ struct SynthXilinxPass : public ScriptPass
 			else if (!nocarry || help_mode)
 				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
-			if (!nomux || help_mode)
-				run("techmap -map +/xilinx/cells_map.v");
-
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
@@ -277,6 +274,9 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
+			if (!nomux || help_mode)
+				run("techmap -map +/xilinx/cells_map.v");
+
 			run("techmap");
 			run("opt -fast");
 		}