From: Tiago Mück <tiago.muck@arm.com>
Date: Sat, 20 Jun 2020 01:25:25 +0000 (-0500)
Subject: mem-ruby: functions for connecting sequencer ports
X-Git-Tag: develop-gem5-snapshot~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f4853012965e74fa420ffabaae4d1bdf3c2fd83;p=gem5.git

mem-ruby: functions for connecting sequencer ports

Added functions for connecting the sequencer and cpu ports.
Using these functions instead of wiring up the ports directly allow
protocols to provide specialized sequencer implementations. For
instance, connecting the cpu icache_port and dcache_port to
different sequencer ports or to different sequencers.

A follow-up patch will update the configurations to use these
functions.

Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 0e23fc0af..f56574c50 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -99,6 +99,32 @@ class RubySequencer(RubyPort):
    # 99 is the dummy default value
    coreid = Param.Int(99, "CorePair core id")
 
+   def connectCpuPorts(self, cpu):
+      """
+      Helper for connecting all cpu memory request output ports to this
+      object's in_ports.
+      This assumes the provided cpu object is an instance of BaseCPU. Non-cpu
+      objects should use connectInstPort and connectDataPort.
+      """
+      import m5.objects
+      assert(isinstance(cpu, m5.objects.BaseCPU))
+      # this connects all cpu mem-side ports to self.in_ports
+      cpu.connectAllPorts(self)
+
+   def connectIOPorts(self, piobus):
+      """
+      Helper for connecting this object's IO request and response ports to the
+      provided bus object. Usually a iobus object is used to wireup IO
+      components in a full system simulation. Incoming/Outgoing IO requests do
+      not go though the SLICC protocol so the iobus must be connected to the
+      sequencer directly.
+      """
+      import m5.defines
+      self.pio_request_port = piobus.cpu_side_ports
+      self.mem_request_port = piobus.cpu_side_ports
+      if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+         self.pio_response_port = piobus.mem_side_ports
+
 class RubyHTMSequencer(RubySequencer):
    type = 'RubyHTMSequencer'
    cxx_class = 'HTMSequencer'