From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Apr 2021 16:58:07 +0000 (+0000)
Subject: different FreePDK45 experiments10 chip size
X-Git-Tag: LS180_RC3~125
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f4c3284be9fbe20e6650cbbcaa36bb6d42f94a4;p=soclayout.git

different FreePDK45 experiments10 chip size
---

diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 10dd423..4acedc7 100644
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -31,8 +31,8 @@ def scriptMain ( **kw ):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
     rvalue = True
-    coreSize   = u(6*90.0)
-    chipBorder = u(2*214.0 + 10*13.0)
+    coreSize   = u(3*90.0)
+    chipBorder = u(4*214.0 + 10*13.0)
     try:
         helpers.setTraceLevel( 550 )
         cell, editor = plugins.kwParseMain( **kw )