From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Oct 2022 16:16:26 +0000 (+0100)
Subject: remove redundant case_dsrd3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f52c161c561a42ac0920ba5e656007a28e7acbf;p=openpower-isa.git

remove redundant case_dsrd3
---

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index f066e40d..6a314212 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -117,20 +117,6 @@ class BigIntCases(TestAccumulatorBase):
                 e.intregs[3] = v % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
-    def case_dsrd3(self):
-        prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False)
-        for sh in _SHIFT_TEST_RANGE:
-            with self.subTest(sh=sh):
-                gprs = [0] * 32
-                gprs[3] = 0x123456789ABCDEF
-                gprs[4] = 0xFEDCBA9876543210
-                gprs[5] = sh % 2 ** 64
-                e = ExpectedState(pc=4, int_regs=gprs)
-                v = gprs[4] << 64
-                v >>= sh % 64
-                e.intregs[3] = v % 2 ** 64
-                self.add_case(prog, gprs, expected=e)
-
 
 class SVP64BigIntCases(TestAccumulatorBase):
     def case_sv_bigint_add(self):