From: Xan Date: Wed, 25 Apr 2018 11:59:01 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5514 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f686ff2c2490bec82e023362f71de6f0a04ec76;p=libreriscv.git --- diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index 61ca490a1..f6dde6311 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -7,7 +7,7 @@ An example use case is a string copy operation - using Harmonised RVP, binary co ## Register file comparison The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16]. -In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations +In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations. | Register | Andes ISA | Harmonised RVP ISA | | ------------------ | ------------------------- | ------------------- | @@ -47,6 +47,9 @@ In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT | v30 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] | | v31 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] | +However, programmers may reconfigure the Harmonised RVP register file if the default configuration is unsuitable. +To keep implementations simple and focused on within-register SIMD only, there is a strict 1:1 mapping between vectors (v0-v31) and integer registers (r0-r31). +Programmers needing forwards compatibility with RV Vector implementations should use VLD and VST to load/store from vector registers (even though these are then mapped into integer registers). ## Proposed Harmonised RVP vector op instruction encoding