From: Palmer Dabbelt Date: Fri, 4 Nov 2016 14:18:06 +0000 (+0000) Subject: Update RISC-V documentation and make sure that it is included in the gas info file. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f7eddc4d1a03c982a4f0361879bc5347b921b10;p=binutils-gdb.git Update RISC-V documentation and make sure that it is included in the gas info file. * Makefile.am (CPU_DOCS): Add c-riscv.texi. * Makefile.in: Regenerate. * doc/all.texi: Set RISCV. * doc/as.texinfo: Add RISCV options. Add RISC-V-Dependent node. Include c-riscv.texi. * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index d6416722b94..1c73f4c5cd2 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2016-11-04 Palmer Dabbelt + Andrew Waterman + + * Makefile.am (CPU_DOCS): Add c-riscv.texi. + * Makefile.in: Regenerate. + * doc/all.texi: Set RISCV. + * doc/as.texinfo: Add RISCV options. + Add RISC-V-Dependent node. + Include c-riscv.texi. + * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts. + 2016-11-03 Graham Markall * testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index 88fa6029f55..54d7ef1b5ca 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -81,6 +81,7 @@ CPU_DOCS = \ c-pj.texi \ c-ppc.texi \ c-rl78.texi \ + c-riscv.texi \ c-rx.texi \ c-s390.texi \ c-score.texi \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index 5f09b6c5812..474bd481cd5 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -355,6 +355,7 @@ CPU_DOCS = \ c-pj.texi \ c-ppc.texi \ c-rl78.texi \ + c-riscv.texi \ c-rx.texi \ c-s390.texi \ c-score.texi \ diff --git a/gas/doc/all.texi b/gas/doc/all.texi index abbca2ff321..3c25d397965 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -63,6 +63,7 @@ @set PJ @set PPC @set RL78 +@set RISCV @set RX @set S390 @set SCORE diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index b1d94d5414e..2b00accc1f2 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -511,6 +511,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mint-register=@var{number}}] [@b{-mgcc-abi}|@b{-mrx-abi}] @end ifset +@ifset RISCV + +@emph{Target RISC-V options:} + [@b{-m32}|@b{-m64}] + [@b{-mrvc}] + [@b{-mhard-float}|@b{-msoft-float}] +@end ifset @ifset S390 @emph{Target s390 options:} @@ -7592,6 +7599,9 @@ subject, see the hardware manufacturer's manual. @ifset RL78 * RL78-Dependent:: RL78 Dependent Features @end ifset +@ifset RISCV +* RISC-V-Dependent:: RISC-V Dependent Features +@end ifset @ifset RX * RX-Dependent:: RX Dependent Features @end ifset @@ -7819,6 +7829,10 @@ family. @include c-rl78.texi @end ifset +@ifset RISCV +@include c-riscv.texi +@end ifset + @ifset RX @include c-rx.texi @end ifset diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 984b75c68fd..8674ff2eb96 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -15,10 +15,10 @@ @cindex RISC-V support @menu -* RISC-V Options:: RISC-V Options +* RISC-V-Opts:: RISC-V Options @end menu -@node RISC-V Options +@node RISC-V-Opts @section Options The following table lists all availiable RISC-V specific options @@ -40,8 +40,8 @@ Enables the C ISA subset for compressed instructions. Select the floating-point ABI, hard-float has F registers while soft-float doesn't. -@cindex @samp{-march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}} option, RISC-V -@item -march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,} +@cindex @samp{-march=ISA} option, RISC-V +@item -march=ISA Select the base isa, as specified by ISA. For example -march=RV32IMA. @end table