From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Oct 2022 10:49:51 +0000 (+0100)
Subject: TODO, sort out remap indices order
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f8d76c48e6563e31977cef1763d97bb07179246;p=openpower-isa.git

TODO, sort out remap indices order
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 19210204..fc89afea 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -405,7 +405,6 @@ def get_idx_map(dec2, name):
     elif name == 'RC':
         if in3_sel == In3Sel.RC.value:
             return 3
-        assert False, "RC does not exist yet"
     elif name in ['EA', 'RS']:
         if in1_sel == In1Sel.RS.value:
             return 1
@@ -2181,12 +2180,25 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         mi2 = self.svstate.mi2
         mo0 = self.svstate.mo0
         mo1 = self.svstate.mo1
-        steps = [(self.dec2.in1_step, mi0),  # RA
-                 (self.dec2.in2_step, mi1),  # RB
-                 (self.dec2.in3_step, mi2),  # RC
-                 (self.dec2.o_step, mo0),   # RT
-                 (self.dec2.o2_step, mo1),   # EA
+        steps = [[self.dec2.in1_step,  mi0],  # RA
+                 [self.dec2.in2_step,  mi1],  # RB
+                 [self.dec2.in3_step,  mi2],  # RC
+                 [self.dec2.o_step,  mo0],   # RT
+                 [self.dec2.o2_step,  mo1],   # EA
                  ]
+        if False: # TODO
+            rnames = ['RA', 'RB', 'RC', 'RT', 'RS']
+            for i, reg in enumerate(rnames):
+                idx = yield from get_idx_map(self.dec2, reg)
+                if idx is None:
+                    idx = yield from get_idx_map(self.dec2, "F"+reg)
+                if idx == 1:  # RA
+                    steps[i][0] = self.dec2.in1_step
+                elif idx == 2: # RB
+                    steps[i][0] = self.dec2.in2_step
+                elif idx == 3: # RC
+                    steps[i][0] = self.dec2.in3_step
+                log("remap step", i, reg, idx, steps[i][1])
         remap_idxs = self.remap_idxs
         rremaps = []
         # now cross-index the required SHAPE for each of 3-in 2-out regs
@@ -2198,10 +2210,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             if shape.value == 0x0:
                 continue
             # now set the actual requested step to the current index
-            yield dstep.eq(remap_idx)
+            if dstep is not None:
+                yield dstep.eq(remap_idx)
 
             # debug printout info
-            rremaps.append((shape.mode, hex(shape.value),
+            rremaps.append((shape.mode, hex(shape.value), dstep,
                             i, rnames[i], shape_idx, remap_idx))
         for x in rremaps:
             log("shape remap", x)
diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py
index 134e803f..787aa990 100644
--- a/src/openpower/decoder/isa/test_caller_svindex.py
+++ b/src/openpower/decoder/isa/test_caller_svindex.py
@@ -526,7 +526,7 @@ class SVSTATETestCase(FHDLTestCase):
             print (sim.gpr.dump())
             self._check_regs(sim, expected_regs)
             self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1
-            self.assertEqual(sim.svstate.SVme, 0b10010) # RS and RB active
+            self.assertEqual(sim.svstate.SVme, 0b00110) # RS and RB active
             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
             self.assertEqual(sim.svstate.mi0, 0) # RS
             self.assertEqual(sim.svstate.mi1, 1) # RB