From: lkcl <lkcl@web>
Date: Tue, 25 Apr 2023 14:18:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4f9debb42a77b38bc054f394058dfa7392a06b7f;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 2f5752c6f..6c1600f86 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -101,8 +101,14 @@ OPF ISA WG):
 
 CW2-Form
 
-* crrweird: RT,BFA,M,fmsk,fmap
-* crrweird.: RT,BFA,M,fmsk,fmap
+```
+    |0     |6   |9 |11|12   |16   |19  |22   |26   |31|
+    | PO   | RT    |M |fmsk |BFA  |XO  |fmap | XO  |Rc|
+
+```
+
+* crrweird RT,BFA,M,fmsk,fmap
+* crrweird. RT,BFA,M,fmsk,fmap
 
 ```
     creg = CR{BFA}
@@ -131,9 +137,15 @@ Special registers altered:
     CR0        (Rc=1)
 ```
 
-**mfcrrweird**
+## mfcrrweird
+
+```
+    |0     |6   |9 |11|12   |16   |19  |22   |26   |31|
+    | PO   | RA    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BT    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BF |  |M |fmsk |BF   |XO  |fmap | XO     |
+```
 
-fmap is encoded in XO and is 4 bits
 
 ```
     mfcrrweird: RT,BFA,fmsk,fmap
@@ -157,9 +169,15 @@ Also as noted below, element-width override bits normally used
 on the source is instead used to allow multiple results to be packed
 into the destination.  *Destination elwidth overrides still apply*
 
-**mtcrrweird**
+## mtcrrweird
+
+```
+    |0     |6   |9 |11|12   |16   |19  |22   |26   |31|
+    | PO   | RA    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BT    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BF |  |M |fmsk |BF   |XO  |fmap | XO     |
+```
 
-fmap is encoded in XO and is 4 bits
 
 ```
     mtcrrweird: BF,RA,M,fmsk,fmap
@@ -182,7 +200,7 @@ Mode capability
 Hardware Architectural Note: when M=1 this instruction is a Read-Modify-Write
 on the `BF` CR Field. When M=0 it is a more normal Write.
 
-**mtcrweird**
+## mtcrweird
 
 ```
     mtcrweird: BF,RA,M,fmsk,fmap
@@ -209,7 +227,14 @@ When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
 type operation that has 3-bit Data-dependent and 3-bit Predicate-result
 capability (BF is 3 bits)
 
-**mcrfm** - Move CR Field, masked.
+## mcrfm - Move CR Field, masked.
+
+```
+    |0     |6   |9 |11|12   |16   |19  |22   |26   |31|
+    | PO   | RA    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BT    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BF |  |M |fmsk |BF   |XO  |fmap | XO     |
+```
 
 This instruction copies, sets, or inverts parts of a CR Field
 into another CR Field.  `mcrf` copies only one bit of the CR
@@ -245,7 +270,14 @@ to BF by ensuring that `fmsk` and `fmap` have the same bit set.  Also,
 individual bits in BF may be set to 1 by ensuring that the required bit of
 `fmsk` is set to zero and the same bit in `fmap` is set to 1*
 
-**crweirder**
+## crweirder
+
+```
+    |0     |6   |9 |11|12   |16   |19  |22   |26   |31|
+    | PO   | RA    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BT    |M |fmsk |BF   |XO  |fmap | XO     |
+    | PO   | BF |  |M |fmsk |BF   |XO  |fmap | XO     |
+```
 
 ```
     crweirder: BT,BFA,fmsk,fmap