From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 19:22:03 +0000 (-0700)
Subject: synth_ice40 to use renamed files
X-Git-Tag: working-ls180~1237^2~212
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4fb9ccfcd81db6d2e574bea3d142b714126d1123;p=yosys.git

synth_ice40 to use renamed files
---

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..91cd063a2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -317,9 +317,9 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
-					run("read_verilog +/ice40/cells_box.v");
+					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else