From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 11 Mar 2014 10:39:30 +0000 (+0100)
Subject: Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
X-Git-Tag: yosys-0.3.0~69
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c;p=yosys.git

Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
---

diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh
index 8285875b8..541da483e 100644
--- a/tests/techmap/mem_simple_4x1_runtest.sh
+++ b/tests/techmap/mem_simple_4x1_runtest.sh
@@ -2,7 +2,7 @@
 
 set -ev
 
-yosys -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
+yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
 
 iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
 iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v