From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 01:23:34 +0000 (-0800)
Subject: Add another test with constant driver
X-Git-Tag: working-ls180~778^2~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154;p=yosys.git

Add another test with constant driver
---

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 271a8edef..a9d3fe672 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -23,3 +23,31 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] b);
+(* submod="bar" *) sub s1(a, b[1]);
+assign b[0] = 1'b0;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+
+submod
+dump
+flatten
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter