From: whitequark <whitequark@whitequark.org>
Date: Tue, 16 Jul 2019 20:57:05 +0000 (+0000)
Subject: write_verilog: dump zero width constants correctly.
X-Git-Tag: working-ls180~1186^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ff44d85a5cb63c7b3f67c2f2398e62db7f199eb;p=yosys.git

write_verilog: dump zero width constants correctly.

Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a020d82b6..48404b34c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -189,7 +189,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	if (width < 0)
 		width = data.bits.size() - offset;
 	if (width == 0) {
-		f << "\"\"";
+		// See IEEE 1364-2005 Clause 5.1.14.
+		f << "{0{1'b0}}";
 		return;
 	}
 	if (nostr)