From: Samuel Pitoiset Date: Wed, 21 Nov 2018 10:34:42 +0000 (+0100) Subject: radv: remove useless sync after CmdClear{Color,DepthStencil}Image() X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ff4af3d91659285e8a4b198546847d8cc82c381;p=mesa.git radv: remove useless sync after CmdClear{Color,DepthStencil}Image() 'post_flush' is only set to NULL for the normal clear path (ie. only vkCmdClearColorImage() and vkCmdClearDepthStencilImage() are affected commands). Because these two operations have to be externally synchronized with VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT, it's useless to set those flags internallY. VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle, while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector caches and L2. RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 will be superseded by RADV_CMD_FLAG_INV_GLOBAL_L2. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 7fdd374afa9..bf88d3a84d9 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -969,8 +969,6 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer, radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects); if (post_flush) { *post_flush |= flush_bits; - } else { - cmd_buffer->state.flush_bits |= flush_bits; } return true; @@ -1453,8 +1451,6 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, if (post_flush) { *post_flush |= flush_bits; - } else { - cmd_buffer->state.flush_bits |= flush_bits; } radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,