From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Feb 2013 22:19:30 +0000 (+0100)
Subject: Fixed "extract" pass for non-optimized needles
X-Git-Tag: yosys-0.2.0~784
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=500786af5584c8a27e75bdf26f123328d9d574bd;p=yosys.git

Fixed "extract" pass for non-optimized needles
---

diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc
index 7541b2603..9b5991bfe 100644
--- a/passes/extract/extract.cc
+++ b/passes/extract/extract.cc
@@ -158,18 +158,17 @@ namespace
 			RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
 			RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
 
-			for (auto &conn : needle_cell->connections)
-				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(conn.second))
-				{
-					RTLIL::SigSpec sig = sigmap(conn.second);
+			for (auto &conn : needle_cell->connections) {
+				RTLIL::SigSpec sig = sigmap(conn.second);
+				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					sig.expand();
-
 					for (int i = 0; i < sig.width; i++)
 					for (auto &port : sig2port.find(sig.chunks[i])) {
 						RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
 						cell->connections.at(port.first).replace(port.second, bitsig);
 					}
 				}
+			}
 
 			haystack->cells.erase(haystack_cell->name);
 			delete haystack_cell;