From: Eddie Hung Date: Thu, 23 Apr 2020 00:26:56 +0000 (-0700) Subject: verific: import enum attributes from verific X-Git-Tag: working-ls180~592^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5028e17f7db11f901ce9e423dfe2c6f7e68259cc;p=yosys.git verific: import enum attributes from verific --- diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 519151310..ae7fcefa7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1153,6 +1153,26 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se for (auto net : anyseq_nets) module->connect(net_map_at(net), module->Anyseq(new_verific_id(net))); + char *id_name; + TypeRange *type_range; + FOREACH_MAP_ITEM(nl->GetTypeRangeTable(), mi, &id_name, &type_range) + { + if (!type_range) + continue; + if (!type_range->IsTypeEnum()) + continue; + auto wire = module->wire(RTLIL::escape_id(id_name)); + log_assert(wire); + wire->set_string_attribute(ID(wiretype), type_range->GetTypeName()); + + MapIter mj; + char *k, *v; + FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mj, &k, &v) { + IdString key = stringf("\\enum_value_%s", v); + wire->set_string_attribute(key, k); + } + } + pool sva_asserts; pool sva_assumes; pool sva_covers;