From: Dave Airlie <airlied@redhat.com>
Date: Mon, 13 Nov 2017 03:05:25 +0000 (+1000)
Subject: r600/shader: reserve first register of vertex shader.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50330d7115f0d5050ec3cfe6bca2b0136222e097;p=mesa.git

r600/shader: reserve first register of vertex shader.

r0 in input into vertex shaders contains things like vertexid,
we need to reserve it even if we have no inputs.

This fixes a bunch of tessellation piglits.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index af866c4bddb..c6e445744ed 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3051,9 +3051,11 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		ctx.file_offset[i] = 0;
 	}
 
-	if (ctx.type == PIPE_SHADER_VERTEX && ctx.info.num_inputs) {
+	if (ctx.type == PIPE_SHADER_VERTEX)  {
+
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
-		r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
+		if (ctx.info.num_inputs)
+			r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
 	}
 	if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		if (ctx.bc->chip_class >= EVERGREEN)