From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Jan 2022 15:19:00 +0000 (+0000)
Subject: missed setting of r0_full to zero in dcache. not encountered as
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=503fdf026884b3e93f51c251ff170d9ccd6ba0a0;p=soc.git

missed setting of r0_full to zero in dcache. not encountered as
a bug but would have done in future
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 3d06ef9b..ee6cc5ca 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -747,6 +747,7 @@ class DCache(Elaboratable):
             comb += r.mmu_req.eq(0)
             comb += r.d_valid.eq(0)
 
+        sync += r0_full.eq(0)
         with m.If((~r1.full & ~d_in.hold) | ~r0_full):
             sync += r0.eq(r)
             sync += r0_full.eq(r.req.valid)