From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 15 Nov 2010 20:04:03 +0000 (-0600)
Subject: ARM: Fix SRS instruction to micro-code memory operation and register update.
X-Git-Tag: stable_2012_02_02~749
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50431f4eabc3894337586ca298a095643b3b6af0;p=gem5.git

ARM: Fix SRS instruction to micro-code memory operation and register update.

Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
---

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index ff98c58d2..c26488eba 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -112,8 +112,6 @@ let {{
             Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
                      ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
             '''
-            if self.writeback:
-                accCode += "SpMode = SpMode + %s;\n" % wbDiff
 
             global header_output, decoder_output, exec_output
 
@@ -122,11 +120,18 @@ let {{
                           "postacc_code": "" }
             codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
 
+            wbDecl = None
+            if self.writeback:
+                wbDecl = '''MicroAddiUop(machInst,
+                              intRegInMode((OperatingMode)regMode, INTREG_SP),
+                              intRegInMode((OperatingMode)regMode, INTREG_SP),
+                              %d);''' % wbDiff
+
             (newHeader,
              newDecoder,
              newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
                  ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
-                 base = 'SrsOp')
+                 'SrsOp', wbDecl)
 
             header_output += newHeader
             decoder_output += newDecoder