From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Fri, 11 Nov 2011 12:36:37 +0000 (-0800)
Subject: Use new compiler toolchain's disassembler
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=504a07f261f25eb884c91b7008f85d669b025cb8;p=riscv-isa-sim.git

Use new compiler toolchain's disassembler
---

diff --git a/configure b/configure
index 2f60541..3426081 100755
--- a/configure
+++ b/configure
@@ -4076,7 +4076,7 @@ $as_echo "#define RISCV_ENABLE_VEC /**/" >>confdefs.h
 
 fi
 
-libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
+libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv-elf/lib/libopcodes.a
 as_ac_File=`$as_echo "ac_cv_file_$libopc" | $as_tr_sh`
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $libopc" >&5
 $as_echo_n "checking for $libopc... " >&6; }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index cce526b..385e329 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -221,6 +221,8 @@ void processor_t::deliver_ipi()
   run = true;
 }
 
+extern "C" int print_insn_little_riscv(bfd_vma, disassemble_info*);
+
 void processor_t::disasm(insn_t insn, reg_t pc)
 {
   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
@@ -229,14 +231,14 @@ void processor_t::disasm(insn_t insn, reg_t pc)
   disassemble_info info;
   INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
   info.flavour = bfd_target_unknown_flavour;
-  info.arch = bfd_arch_mips;
-  info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
+  info.arch = bfd_architecture(25); // bfd_arch_riscv
+  info.mach = 164; // bfd_mach_riscv_rocket64
   info.endian = BFD_ENDIAN_LITTLE;
   info.buffer = (bfd_byte*)&insn;
   info.buffer_length = sizeof(insn);
   info.buffer_vma = pc;
 
-  int ret = print_insn_little_mips(pc, &info);
+  int ret = print_insn_little_riscv(pc, &info);
   assert(ret == insn_length(insn.bits));
   #else
   printf("unknown");
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 2919277..636a8c4 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -18,7 +18,7 @@ AS_IF([test "x$enable_vec" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
 ])
 
-libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
+libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv-elf/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])
 
 libbfd="/opt/local/lib/libbfd.dylib"