From: Anonymous Maarten <anonymous.maarten@gmail.com>
Date: Wed, 17 Jun 2020 11:52:45 +0000 (+0200)
Subject: MSVC does not understand __builtin_unreachable
X-Git-Tag: working-ls180~467^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=504f22061995d5b0ad6549e360ee1dded0e86116;p=yosys.git

MSVC does not understand __builtin_unreachable
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 7905ea598..ea23139e2 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -591,7 +591,7 @@ read_define_args()
 
 		default:
 			// The only FSM states are 0-2 and we dealt with 2 at the start of the loop.
-			__builtin_unreachable();
+			log_assert(false);
 		}
 	}