From: lkcl Date: Fri, 8 Oct 2021 23:35:09 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3693 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5058ca3683a3d8690f155bb8b46bfcd5901cdf30;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index 91fa3c8e2..17d6470dd 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -275,7 +275,9 @@ achieve then **almost no modifications to nmigen would be required** because dsl.Module is *already* 99% abstracted in terms of the lower-level Type 1 (ast.*) constructs. -Analysis of the internals of nmigen shows that m.If, m.Else, m.FSM and m.Switch are all redirected to ast.py `Switch`. Within that function Mux and other "global" functions (similar to python operator functions). The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed. +Analysis of the internals of nmigen shows that m.If, m.Else, m.FSM and m.Switch are all redirected to ast.py `Switch`. Within that ast.Switch +function only asy.Mux and other Type 1 (AST) "global" functions +similar to python operator are used. The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed.