From: Clifford Wolf Date: Thu, 22 Aug 2013 18:26:19 +0000 (+0200) Subject: Added simple xilinx7 technology mapping files X-Git-Tag: yosys-0.2.0~486 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5059b3166098044a87b3d0b7f3ae2957df7e6194;p=yosys.git Added simple xilinx7 technology mapping files --- diff --git a/techlibs/xilinx7/cells.v b/techlibs/xilinx7/cells.v new file mode 100644 index 000000000..8c8b9c759 --- /dev/null +++ b/techlibs/xilinx7/cells.v @@ -0,0 +1,53 @@ +module \$_DFF_P_ (D, C, Q); + + input D, C; + output Q; + + FDRE fpga_dff ( + .D(D), .Q(Q), .C(C), + .CE(1'b1), .R(1'b0) + ); + +endmodule + +module \$lut (I, O); + + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] I; + output O; + + generate + if (WIDTH == 1) begin:lut1 + LUT1 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0])); + end else + if (WIDTH == 2) begin:lut2 + LUT2 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1])); + end else + if (WIDTH == 3) begin:lut3 + LUT3 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2])); + end else + if (WIDTH == 4) begin:lut4 + LUT4 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3])); + end else + if (WIDTH == 5) begin:lut5 + LUT5 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3]), .I4(I[4])); + end else + if (WIDTH == 6) begin:lut6 + LUT6 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3]), .I4(I[4]), .I5(I[5])); + end else begin:error + wire TECHMAP_FAIL; + end + endgenerate + +endmodule diff --git a/techlibs/xilinx7/counter.v b/techlibs/xilinx7/counter.v new file mode 100644 index 000000000..72208bd80 --- /dev/null +++ b/techlibs/xilinx7/counter.v @@ -0,0 +1,12 @@ +module counter (clk, rst, en, count); + + input clk, rst, en; + output reg [3:0] count; + + always @(posedge clk) + if (rst) + count <= 4'd0; + else if (en) + count <= count + 4'd1; + +endmodule diff --git a/techlibs/xilinx7/counter_tb.v b/techlibs/xilinx7/counter_tb.v new file mode 100644 index 000000000..b6b64269e --- /dev/null +++ b/techlibs/xilinx7/counter_tb.v @@ -0,0 +1,61 @@ +`timescale 1 ns / 1 ps + +module testbench; + +reg clk, en, rst; +wire [3:0] count; + +counter uut_counter( + .clk(clk), + .count(count), + .en(en), + .rst(rst) +); + +initial begin + clk <= 0; + forever begin + #50; + clk <= ~clk; + end +end + +initial begin + @(posedge clk); + forever begin + @(posedge clk); + $display("%d", count); + end +end + +initial begin + rst <= 1; en <= 0; @(posedge clk); + rst <= 1; en <= 0; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 1; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 1; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + rst <= 0; en <= 1; @(posedge clk); + rst <= 0; en <= 0; @(posedge clk); + $finish; +end + +endmodule diff --git a/techlibs/xilinx7/run_testbench.sh b/techlibs/xilinx7/run_testbench.sh new file mode 100644 index 000000000..970fef46c --- /dev/null +++ b/techlibs/xilinx7/run_testbench.sh @@ -0,0 +1,41 @@ +#!/bin/bash + +set -ex + +XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/ + +../../yosys - <<- EOT + # read design + read_verilog counter.v + + # high-level synthesis + hierarchy -check -top counter + proc; opt; fsm; opt; techmap; opt + + # mapping logic to LUTs using Berkeley ABC + abc -lut 6; opt + + # map internal cells to FPGA cells + techmap -map cells.v; opt + + # write netlist + write_verilog -noattr testbench_synth.v +EOT + +iverilog -o testbench_gold counter_tb.v counter.v +iverilog -o testbench_gate counter_tb.v testbench_synth.v \ + $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v + +./testbench_gold > testbench_gold.txt +./testbench_gate > testbench_gate.txt + +if diff -u testbench_gold.txt testbench_gate.txt; then + set +x; echo; echo; banner " PASS " +else + exit 1 +fi + +if [ "$*" = "-clean" ]; then + rm -f testbench_{synth.v,{gold,gate}{,.txt}} +fi +