From: lkcl Date: Fri, 25 Dec 2020 13:55:46 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~918 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50636c0f7e4e93a0d8ea5699e0ddbb0572265503;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 4585590ee..c5f2f1c04 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -24,7 +24,7 @@ The fundamentals are: * Once the loop is completed *only then* is the Program Counter allowed to move to the next instruction. -Hardware (and simulator)implementors are free and clear to implement this as literally a for-loop, sitting in between instruction decode and issue. Higher performance systems may deploy SIMD backends and multi-issue, although it is strongly recommended to add predication capability into all SIMD backend units. +Hardware (and simulator) implementors are free and clear to implement this as literally a for-loop, sitting in between instruction decode and issue. Higher performance systems may deploy SIMD backends and multi-issue, although it is strongly recommended to add predication capability into all SIMD backend units. In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source and destination have been "tagged" as Vectors, is simply: