From: lkcl <lkcl@web>
Date: Sat, 12 Dec 2020 18:23:17 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1378
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=506a4f5db83e59b7fa31adb8f1d61e7d9f70ea2e;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 6b8afe2bf..401fc3498 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -39,7 +39,7 @@ mode:
 
 * zmode: 2 bit src pred zero mode, dest pred zero mode
 * ffirst: 3 bit.  EN (and CR index bit 0-3, applicable when Rc=1).
-   operations that do not have Rc may take bit 1 to mean "invert test"
+   operations that do not have Rc or when Rc=0 may take bit 1 to mean " zero ir nonzero".
 
 ## twin predication, CR based.