From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 4 Dec 2013 08:10:16 +0000 (+0100)
Subject: Added support for local regs in named blocks
X-Git-Tag: yosys-0.2.0~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=507c63d112658b658cc1f1fbbcbb20edc212294c;p=yosys.git

Added support for local regs in named blocks
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 1453d13a9..e9c689ac2 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -576,6 +576,10 @@ struct AST_INTERNAL::ProcessGenerator
 			}
 			break;
 
+		case AST_WIRE:
+			log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
+			break;
+
 		case AST_TCALL:
 		case AST_FOR:
 			break;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 80cf230e6..0a32e9506 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -350,6 +350,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			break;
 		if (type == AST_GENBLOCK)
 			break;
+		if (type == AST_BLOCK && !str.empty())
+			break;
 		if (type == AST_PREFIX && i >= 1)
 			break;
 		while (did_something_here && i < children.size()) {
@@ -678,6 +680,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		did_something = true;
 	}
 
+	// transform block with name
+	if (type == AST_BLOCK && !str.empty())
+	{
+		std::map<std::string, std::string> name_map;
+		expand_genblock(std::string(), str + ".", name_map);
+
+		std::vector<AstNode*> new_children;
+		for (size_t i = 0; i < children.size(); i++)
+			if (children[i]->type == AST_WIRE) {
+				children[i]->simplify(false, false, false, stage, -1, false);
+				current_ast_mod->children.push_back(children[i]);
+			} else
+				new_children.push_back(children[i]);
+
+		children.swap(new_children);
+		did_something = true;
+		str.clear();
+	}
+
 	// simplify unconditional generate block
 	if (type == AST_GENBLOCK && children.size() != 0)
 	{
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 1ffa4e942..5a45a7761 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -407,7 +407,6 @@ opt_signed:
 	};
 
 task_func_body:
-	task_func_body wire_decl |
 	task_func_body behavioral_stmt |
 	/* empty */;
 
@@ -761,7 +760,7 @@ simple_behavioral_stmt:
 
 // this production creates the obligatory if-else shift/reduce conflict
 behavioral_stmt:
-	defattr |
+	defattr | wire_decl |
 	simple_behavioral_stmt ';' |
 	hierarchical_id attr {
 		AstNode *node = new AstNode(AST_TCALL);
@@ -778,7 +777,11 @@ behavioral_stmt:
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 		append_attr(node, $1);
+		if ($3 != NULL)
+			node->str = *$3;
 	} behavioral_stmt_list TOK_END opt_label {
+		if ($3 != NULL && $7 != NULL && *$3 != *$7)
+			frontend_verilog_yyerror("Syntax error.");
 		if ($3 != NULL)
 			delete $3;
 		if ($7 != NULL)