From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 Jun 2019 13:47:24 +0000 (+0100)
Subject: add immediate arg to instr
X-Git-Tag: div_pipeline~1901
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5080334513c63819b3c8d522e2cd334ebc2d0307;p=soc.git

add immediate arg to instr
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 47101d1e..9afdf065 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -190,7 +190,8 @@ class CompUnitALUs(CompUnitsBase):
 
         units = []
         for alu in [add, sub, mul, shf]:
-            units.append(ComputationUnitNoDelay(rwid, 2, alu))
+            aluopwid = 3 # extra bit for immediate mode
+            units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
 
         CompUnitsBase.__init__(self, rwid, units)
 
@@ -198,9 +199,9 @@ class CompUnitALUs(CompUnitsBase):
         m = CompUnitsBase.elaborate(self, platform)
         comb = m.d.comb
 
-        # hand the same operation to all units
+        # hand the same operation to all units, only lower 2 bits though
         for alu in self.units:
-            comb += alu.oper_i.eq(self.oper_i)
+            comb += alu.oper_i[0:2].eq(self.oper_i)
 
         return m
 
@@ -372,7 +373,7 @@ class Scoreboard(Elaboratable):
 
         # Int ALUs and Comp Units
         n_int_alus = 5
-        cua = CompUnitALUs(self.rwid, 2)
+        cua = CompUnitALUs(self.rwid, 3)
         cub = CompUnitBR(self.rwid, 2)
         m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
         bgt = cub.bgt # get at the branch computation unit
@@ -653,6 +654,7 @@ class IssueToScoreboard(Elaboratable):
             src1 = iq.data_o[0].src1_i
             src2 = iq.data_o[0].src2_i
             op = iq.data_o[0].oper_i
+            opi = iq.data_o[0].opim_i # immediate set
 
             # set the src/dest regs
             comb += sc.int_dest_i.eq(dest)
@@ -667,7 +669,7 @@ class IssueToScoreboard(Elaboratable):
                 comb += wait_issue_br.eq(1)
             with m.Else():                   # alu
                 comb += sc.aluissue.insn_i.eq(1)
-                comb += sc.alu_oper_i.eq(op & 0x3)
+                comb += sc.alu_oper_i.eq(Cat(op & 0x3, opi))
                 comb += wait_issue_alu.eq(1)
 
             # XXX TODO
diff --git a/src/scoreboard/instruction_q.py b/src/scoreboard/instruction_q.py
index 1f582b74..65496a6a 100644
--- a/src/scoreboard/instruction_q.py
+++ b/src/scoreboard/instruction_q.py
@@ -12,6 +12,7 @@ class Instruction(RecordObject):
         RecordObject.__init__(self, name=name)
         self.oper_i = Signal(opwid, reset_less=True)
         self.opim_i = Signal(1, reset_less=True) # src2 is an immediate
+        self.imm_i = Signal(wid, reset_less=True)
         self.dest_i = Signal(wid, reset_less=True)
         self.src1_i = Signal(wid, reset_less=True)
         self.src2_i = Signal(wid, reset_less=True)
diff --git a/src/scoreboard/test_iq.py b/src/scoreboard/test_iq.py
index 5a059831..94ceac7e 100644
--- a/src/scoreboard/test_iq.py
+++ b/src/scoreboard/test_iq.py
@@ -96,7 +96,9 @@ def mk_insns(n_insns, wid, opwid):
         op2 = randint(0, (1<<wid)-1)
         dst = randint(0, (1<<wid)-1)
         oper = randint(0, (1<<opwid)-1)
-        res.append({'oper_i': oper, 'opim_i': opi, 'dest_i': dst,
+        imm = randint(0, (1<<wid)-1)
+        res.append({'oper_i': oper, 'opim_i': opi, 
+                    'imm_i': imm, 'dest_i': dst,
                     'src1_i': op1, 'src2_i': op2})
     return res