From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 5 Dec 2016 21:48:23 +0000 (-0500)
Subject: mem: Ensure InvalidateReq is considered isForward by MSHRs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50812a20f1f92782f6d8f4976ce39753e7c0864d;p=gem5.git

mem: Ensure InvalidateReq is considered isForward by MSHRs

This patch fixes an issue where an MSHR would incorrectly be perceived
to provide data to targets arriving after an InvalidateReq. To address
this the InvalidateReq is now treated as isForward, much like an
UpgradeReq that did not hit in the cache.

Change-Id: Ia878444d949539b5c33fd19f3e12b0b8a872275e
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
---

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index a3211b0b4..6f02edb82 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -909,7 +909,8 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
     bool blkValid = blk && blk->isValid();
 
     if (cpu_pkt->req->isUncacheable() ||
-        (!blkValid && cpu_pkt->isUpgrade())) {
+        (!blkValid && cpu_pkt->isUpgrade()) ||
+        cpu_pkt->cmd == MemCmd::InvalidateReq) {
         // uncacheable requests and upgrades from upper-level caches
         // that missed completely just go through as is
         return nullptr;
@@ -936,8 +937,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
         // where the determination the StoreCond fails is delayed due to
         // all caches not being on the same local bus.
         cmd = MemCmd::SCUpgradeFailReq;
-    } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
-               cpu_pkt->cmd == MemCmd::InvalidateReq) {
+    } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
         // forward as invalidate to all other caches, this gives us
         // the line in Exclusive state, and invalidates all other
         // copies