From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 7 Aug 2020 10:33:06 +0000 (+0200)
Subject: gram.phy.ecp5ddrphy: Remove internal signal for delay
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5082e81c5bde9e46933d458f9a088bdd811dca78;p=gram.git

gram.phy.ecp5ddrphy: Remove internal signal for delay
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index a7d1764..ccea0ea 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -38,13 +38,12 @@ class ECP5DDRPHYInit(Elaboratable):
 
         # DDRDLLA instance -------------------------------------------------------------------------
         _lock = Signal()
-        delay = Signal()
         m.submodules += Instance("DDRDLLA",
             i_CLK=ClockSignal("sync2x"),
             i_RST=ResetSignal("init"),
             i_UDDCNTLN=~update,
             i_FREEZE=freeze,
-            o_DDRDEL=delay,
+            o_DDRDEL=self.delay,
             o_LOCK=_lock)
         lock = Signal()
         lock_d = Signal()
@@ -70,8 +69,6 @@ class ECP5DDRPHYInit(Elaboratable):
         # Wait DDRDLLA Lock
         m.d.comb += tl.trigger.eq(new_lock)
 
-        m.d.comb += self.delay.eq(delay)
-
         return m