From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 19 May 2020 21:55:54 +0000 (+0100)
Subject: output ilang to branch_pipeline.il for branch
X-Git-Tag: div_pipeline~1056
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=508948f55c598a86c2fc401ef49f5c08da22c1f5;hp=20e3e5b60cf2877a25920140304ae3674b7f8888;p=soc.git

output ilang to branch_pipeline.il for branch
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 898afa8d..8666a416 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -104,7 +104,7 @@ class BranchTestCase(FHDLTestCase):
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = BranchBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
-        with open("logical_pipeline.il", "w") as f:
+        with open("branch_pipeline.il", "w") as f:
             f.write(vl)