From: Vincent Lejeune Date: Mon, 8 Oct 2012 13:37:39 +0000 (+0200) Subject: radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5090ce42e4437a2f9d1043309417b3fa930ee330;p=mesa.git radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf Reviewed-by: Tom Stellard --- diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 7d4ce610847..d37df6b986a 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -139,8 +139,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, Op.getOperand(2)); case AMDGPUIntrinsic::AMDIL_round_nearest: return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); - case AMDGPUIntrinsic::AMDIL_round_posinf: - return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); } } diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td b/src/gallium/drivers/radeon/AMDILIntrinsics.td index 213c8bbfbb7..3f9e20f0c85 100644 --- a/src/gallium/drivers/radeon/AMDILIntrinsics.td +++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td @@ -146,8 +146,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in { UnaryIntFloat; def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">, UnaryIntFloat; - def int_AMDIL_round_posinf : GCCBuiltin<"__amdil_round_posinf">, - UnaryIntFloat; def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">, UnaryIntFloat; def int_AMDIL_acos : GCCBuiltin<"__amdil_acos">, diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 3b251938774..57ec372d097 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -1117,8 +1117,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf"; bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args; bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq"; - bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf."; + bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly; + bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";