From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 13 May 2020 22:47:44 +0000 (-0400)
Subject: Add test for random rlcd(l/r) instructions
X-Git-Tag: div_pipeline~1242
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=509b5e7a1a36c6a988b62c14b0ddd278655d3954;p=soc.git

Add test for random rlcd(l/r) instructions
---

diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py
index 6eae89a6..e1ca7fc5 100644
--- a/src/soc/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/shift_rot/test/test_pipe_caller.py
@@ -166,6 +166,17 @@ class ALUTestCase(FHDLTestCase):
         initial_regs[1] = random.randint(0, (1<<64)-1)
         self.run_tst_program(Program(lst), initial_regs)
 
+    def test_rlc(self):
+        insns = ["rldic", "rldicl", "rldicr"]
+        for i in range(20):
+            choice = random.choice(insns)
+            sh = random.randint(0, 63)
+            m = random.randint(0, 63)
+            lst = [f"{choice} 3, 1, {sh}, {m}"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         rec = CompALUOpSubset()