From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 18:23:50 +0000 (-0700)
Subject: Forgot one
X-Git-Tag: working-ls180~1104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=509c353fe981c95ca667a637bf2b47477962a60b;p=yosys.git

Forgot one
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e3897d9a6..3ad96d7fb 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -325,7 +325,8 @@ module RAM64X1D (
   (* abc_scc_break *)
   input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );