From: Gabe Black Date: Sat, 26 Sep 2020 23:00:35 +0000 (-0700) Subject: arm,base,gpu: Use std::make_unique instead of m5::make_unique. X-Git-Tag: develop-gem5-snapshot~712 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50a0b85367859ab6c67a772f76fc1825126b2c8d;p=gem5.git arm,base,gpu: Use std::make_unique instead of m5::make_unique. Now that we're using c++14, we can just assume that std::make_unique exists. We no longer have to conditionally inject our own version. Change-Id: I5d851afb02dd05c7af93864ffec3b3184f3d4ec8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35215 Reviewed-by: Daniel Carvalho Maintainer: Gabe Black Tested-by: kokoro --- diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc index 3969b6d5d..b7729b43f 100644 --- a/src/arch/arm/tracers/tarmac_record.cc +++ b/src/arch/arm/tracers/tarmac_record.cc @@ -37,6 +37,8 @@ #include "arch/arm/tracers/tarmac_record.hh" +#include + #include "arch/arm/insts/static_inst.hh" #include "tarmac_tracer.hh" @@ -291,7 +293,7 @@ TarmacTracerRecord::addInstEntry(std::vector& queue, // Generate an instruction entry in the record and // add it to the Instruction Queue queue.push_back( - m5::make_unique(tarmCtx, predicate) + std::make_unique(tarmCtx, predicate) ); } @@ -304,9 +306,9 @@ TarmacTracerRecord::addMemEntry(std::vector& queue, // Memory Queue if (getMemValid()) { queue.push_back( - m5::make_unique(tarmCtx, - static_cast(getSize()), - getAddr(), getIntData()) + std::make_unique(tarmCtx, + static_cast(getSize()), + getAddr(), getIntData()) ); } } @@ -326,9 +328,7 @@ TarmacTracerRecord::addRegEntry(std::vector& queue, // Copying the entry and adding it to the "list" // of entries to be dumped to trace. - queue.push_back( - m5::make_unique(single_reg) - ); + queue.push_back(std::make_unique(single_reg)); } // Gem5 is treating CPSR flags as separate registers (CC registers), diff --git a/src/arch/arm/tracers/tarmac_record.hh b/src/arch/arm/tracers/tarmac_record.hh index bb7a336c2..e5179ceca 100644 --- a/src/arch/arm/tracers/tarmac_record.hh +++ b/src/arch/arm/tracers/tarmac_record.hh @@ -43,6 +43,8 @@ #ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__ #define __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__ +#include + #include "arch/arm/tracers/tarmac_base.hh" #include "base/printable.hh" #include "config/the_isa.hh" @@ -246,7 +248,7 @@ class TarmacTracerRecord : public TarmacBaseRecord if (cpsr_it == queue.end()) { RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR); queue.push_back( - m5::make_unique( + std::make_unique( genRegister(tarmCtx, reg)) ); } diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc index fa4304f33..f4bb7fd3f 100644 --- a/src/arch/arm/tracers/tarmac_record_v8.cc +++ b/src/arch/arm/tracers/tarmac_record_v8.cc @@ -37,6 +37,8 @@ #include "arch/arm/tracers/tarmac_record_v8.hh" +#include + #include "arch/arm/insts/static_inst.hh" #include "arch/arm/tlb.hh" #include "arch/arm/tracers/tarmac_tracer.hh" @@ -185,7 +187,7 @@ TarmacTracerRecordV8::addInstEntry(std::vector& queue, // Generate an instruction entry in the record and // add it to the Instruction Queue queue.push_back( - m5::make_unique(tarmCtx, predicate) + std::make_unique(tarmCtx, predicate) ); } @@ -198,9 +200,9 @@ TarmacTracerRecordV8::addMemEntry(std::vector& queue, // Memory Queue if (getMemValid()) { queue.push_back( - m5::make_unique(tarmCtx, - static_cast(getSize()), - getAddr(), getIntData()) + std::make_unique(tarmCtx, + static_cast(getSize()), + getAddr(), getIntData()) ); } } @@ -220,9 +222,7 @@ TarmacTracerRecordV8::addRegEntry(std::vector& queue, // Copying the entry and adding it to the "list" // of entries to be dumped to trace. - queue.push_back( - m5::make_unique(single_reg) - ); + queue.push_back(std::make_unique(single_reg)); } // Gem5 is treating CPSR flags as separate registers (CC registers), diff --git a/src/base/compiler.hh b/src/base/compiler.hh index 1eaebc802..e2e777f9b 100644 --- a/src/base/compiler.hh +++ b/src/base/compiler.hh @@ -88,28 +88,4 @@ #define M5_NODISCARD #endif -// std::make_unique redefined for C++11 compilers -namespace m5 -{ - -#if __cplusplus >= 201402L // C++14 - -using std::make_unique; - -#else // C++11 - -/** Defining custom version of make_unique: m5::make_unique<>() */ -template -std::unique_ptr -make_unique( Args&&... constructor_args ) -{ - return std::unique_ptr( - new T( std::forward(constructor_args)... ) - ); -} - -#endif // __cplusplus >= 201402L - -} //namespace m5 - #endif // __BASE_COMPILER_HH__ diff --git a/src/gpu-compute/gpu_dyn_inst.hh b/src/gpu-compute/gpu_dyn_inst.hh index 3d2fa0d3f..f34eff6c1 100644 --- a/src/gpu-compute/gpu_dyn_inst.hh +++ b/src/gpu-compute/gpu_dyn_inst.hh @@ -35,6 +35,7 @@ #define __GPU_DYN_INST_HH__ #include +#include #include #include "base/amo.hh" @@ -255,27 +256,27 @@ class GPUDynInst : public GPUExecContext makeAtomicOpFunctor(c0 *reg0, c0 *reg1) { if (isAtomicAnd()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicOr()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicXor()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicCAS()) { - return m5::make_unique>(*reg0, *reg1, cu); + return std::make_unique>(*reg0, *reg1, cu); } else if (isAtomicExch()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicAdd()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicSub()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicInc()) { - return m5::make_unique>(); + return std::make_unique>(); } else if (isAtomicDec()) { - return m5::make_unique>(); + return std::make_unique>(); } else if (isAtomicMax()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else if (isAtomicMin()) { - return m5::make_unique>(*reg0); + return std::make_unique>(*reg0); } else { fatal("Unrecognized atomic operation"); }