From: whitequark <whitequark@whitequark.org>
Date: Thu, 3 Oct 2019 06:10:43 +0000 (+0000)
Subject: [breaking-change] Fix polarity of "dm" signal in "memory" resource.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50acf4a72433a22bbe6a8162deb7b959370a0a15;p=nmigen-boards.git

[breaking-change] Fix polarity of "dm" signal in "memory" resource.

LB# and UB# enable writing their corresponding byte. The "m" in "dm"
means mask; that is, logical high masks (prevents) the byte from
being written. This means that it should use Pins(), not PinsN(),
to get the behavior implied by "mask".
---

diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
index 809035c..33976a7 100644
--- a/nmigen_boards/resources/memory.py
+++ b/nmigen_boards/resources/memory.py
@@ -90,7 +90,7 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
     io.append(Subsignal("a", Pins(a, dir="o")))
     io.append(Subsignal("d", Pins(d, dir="io")))
     if dm is not None:
-        io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
+        io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#"
     if attrs is not None:
         io.append(attrs)
     return Resource.family(*args, default_name="sram", ios=io)