From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Jan 2019 14:05:23 +0000 (+0100)
Subject: Fix VerificImporter asymmetric memories error message
X-Git-Tag: yosys-0.9~351
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50b09de03320843660636c663629c649ab242321;p=yosys.git

Fix VerificImporter asymmetric memories error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 61d9d593c..5280a2b9c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1201,7 +1201,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		{
 			RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
 			if (memory->width != int(inst->Input2Size()))
-				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
+				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
 
 			RTLIL::SigSpec addr = operatorInput1(inst);
 			RTLIL::SigSpec data = operatorInput2(inst);