From: Francisco Jerez <currojerez@riseup.net>
Date: Thu, 3 Sep 2015 14:08:16 +0000 (+0300)
Subject: i965: Adjust gen check in can_do_pipelined_register_writes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50c2713726f007b988502ed5e7073fae11409853;p=mesa.git

i965: Adjust gen check in can_do_pipelined_register_writes

Allow for pipelined register writes for gen < 7.

v2:
 * Split from another patch and adjust comment (jljusten)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg  <krh@bitplanet.net>
---

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index bec318ffa3d..8a1ec324e2c 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -38,8 +38,11 @@
 static bool
 can_do_pipelined_register_writes(struct brw_context *brw)
 {
-   /* Supposedly, Broadwell just works. */
-   if (brw->gen >= 8)
+   /**
+    * gen >= 8 specifically allows these writes. gen <= 6 also
+    * doesn't block them.
+    */
+   if (brw->gen != 7)
       return true;
 
    static int result = -1;