From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 16:29:38 +0000 (+0100) Subject: copy over svstate from core state in PowerDecoder2 X-Git-Tag: 0.0.3~92 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50d3744a213d94cfbf6c3f69c7c9d58ab2d81bba;p=openpower-isa.git copy over svstate from core state in PowerDecoder2 add SVSRR0 to FastRegsEnum --- diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 91a9b502..961929a8 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -300,7 +300,8 @@ class FastRegsEnum: XER = 5 # non-XER bits DEC = 6 TB = 7 - N_REGS = 8 # maximum number of regs + SVSRR0 = 8 + N_REGS = 9 # maximum number of regs # XER Regfile class XERRegsEnum: diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 63b0796b..b18906b8 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -796,7 +796,7 @@ class PowerDecodeSubset(Elaboratable): comb = m.d.comb state = self.state op, do = self.dec.op, self.do - msr, cia = state.msr, state.pc + msr, cia, svstate = state.msr, state.pc, state.svstate # fill in for a normal instruction (not an exception) # copy over if non-exception, non-privileged etc. is detected if not self.final: @@ -823,6 +823,7 @@ class PowerDecodeSubset(Elaboratable): # copy "state" over comb += self.do_copy("msr", msr) comb += self.do_copy("cia", cia) + comb += self.do_copy("svstate", svstate) # set up instruction type # no op: defaults to OP_ILLEGAL @@ -1336,6 +1337,7 @@ class PowerDecode2(PowerDecodeSubset): comb += self.do_copy("ldst_exc", ldst_exc, True) # request type comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state" comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state" + comb += self.do_copy("svstate", self.state.svstate, True) # SVSTATE