From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 02:52:03 +0000 (-0800)
Subject: Fix RAM64M model to have 6 bit address bus
X-Git-Tag: working-ls180~921^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50e0c835606a94c825079a63fc026c906c9985e0;p=yosys.git

Fix RAM64M model to have 6 bit address bus
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3ed0759db..56eb782c6 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1185,10 +1185,10 @@ module RAM64M (
   output DOB,
   output DOC,
   output DOD,
-  input [4:0] ADDRA,
-  input [4:0] ADDRB,
-  input [4:0] ADDRC,
-  input [4:0] ADDRD,
+  input [5:0] ADDRA,
+  input [5:0] ADDRB,
+  input [5:0] ADDRC,
+  input [5:0] ADDRD,
   input DIA,
   input DIB,
   input DIC,