From: Chung-Ju Wu <jasonwucj@gmail.com>
Date: Thu, 5 Apr 2018 03:05:45 +0000 (+0000)
Subject: [NDS32] Add divsi4 and udivsi4 patterns.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50ea1e4ad5f0b926799f935115dcdcb128a4764e;p=gcc.git

[NDS32] Add divsi4 and udivsi4 patterns.

gcc/
	* config/nds32/nds32.md (divsi4, udivsi4): New patterns.

From-SVN: r259119
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb27056da93..485c59ea797 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2018-04-05  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+	* config/nds32/nds32.md (divsi4, udivsi4): New patterns.
+
 2018-04-05  Chung-Ju Wu  <jasonwucj@gmail.com>
 
 	* config/nds32/nds32.md (negsi2): Refine pattern.
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index f69dd9de92f..2d0f1d3e91b 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -535,6 +535,26 @@
   [(set_attr "type"   "div")
    (set_attr "length"   "4")])
 
+;; divsr/divr will keep quotient only when quotient and remainder is the same
+;; register in our ISA spec, it's can reduce 1 register presure if we don't
+;; want remainder.
+(define_insn "divsi4"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(div:SI (match_operand:SI 1 "register_operand" " r")
+		(match_operand:SI 2 "register_operand" " r")))]
+  ""
+  "divsr\t%0, %0, %1, %2"
+  [(set_attr "type"   "div")
+   (set_attr "length"   "4")])
+
+(define_insn "udivsi4"
+  [(set (match_operand:SI 0 "register_operand"          "=r")
+	(udiv:SI (match_operand:SI 1 "register_operand" " r")
+		 (match_operand:SI 2 "register_operand"  " r")))]
+  ""
+  "divr\t%0, %0, %1, %2"
+  [(set_attr "type"   "div")
+   (set_attr "length"   "4")])
 
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